View SMB110_3380563.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SMB110 preliminary information ? summit microelectronics, inc. 2005 1717 fox drive ? san jose ca 95131 ? phone 408 436-9890 ? fax 408 436-9897 http://www.summitmicro.com/ 2099 2.3 5/3/2005 1 five channel programmable dc-dc system power manager introduction ? digital programming of all major parameters via i 2 c interface and non-volatile memory o output voltage set point o output power-up/down sequencing o input/battery voltage monitoring o digital soft-start and output slew rate o output voltage margining o uv/ov monitoring of all outputs o enable/disable outputs independently ? five output channels o two synchronous step-down (buck) channels o one step-up (boost) channel o one inverting (buck-boost) channel o one fixed output +3.3v ldo ? user friendly graphical user interface (gui) ? +2.7v to +6.0v input range ? highly accurate reference and output voltage (<0.5%) with active dc output control (adoc?) technology ? undervoltage lockout (uvlo) with hysteresis ? 800 khz operating frequency ? 96 bytes of user configurable nonvolatile memory applications ? digital camcorders/still cameras ? portable dvd/mp3/gps ? camera/smart phones ? tft displays/monitors/tv?s ? mobile computing/pda?s ? consumer battery-operated equipment the SMB110 is a highly integrated and flexible five-channel power manager designed for use in a wide range of portable applications. the built-in digita l programmability allows system designers to custom tailor the device to suit almost any multi- channel power supply application from digital camcorders to mobile phones. complete with a user friendly gui, all programmable settings including output voltages and input/output voltage monitoring can be customized with ease. the SMB110 integrates all the essential blocks required to implement a complete five-channel power subsystem including two synchronous step-down ?buck? controllers, one step-up ?boost? controller, one inverting ? buck-boost? controller and one fixed output +3.3v ldo. additionally sophisticated power control/monitoring functions required by complex systems are built-in. these include digita lly programmable output voltage set point, power-up/down sequencing, enable/disable, margining and uv/ov/input/output monitoring on all channels. the integration of feat ures and built-in flexibility of the SMB110 allows the system designer to create a ?platform solution? that can be easily modified via software without major hardware changes. combined with the re-programmability of the SMB110 this facilitates rapid design cycles and proliferation from a base design to future generations of product. the SMB110 is suited to battery-powered applications with an input range of +2.7v to +6.0v. output voltages are extremely accurate (<0.5%) employing proprietary adoc? technology. communication is via the industry standard i 2 c bus. all user- programmed settings are stored in non-volatile eeprom of which 96 bytes may be used for general-purpose memory applications. the operating tem perature range is +0c to +70c and the available package is a lead-free, green, rohs compliant, 32-pad qfn-32. simplified applications drawing features & applications figure 1 ? applications diagram featuring the SMB110 five - channel, programmable dc-dc controlle r note: this is an applications example only. some pins, components and values are not shown. SMB110 -0.8v to -30v (prog.) @up to1a vin to +30v (prog.) @ up to 1a +2.7v to +6.0v or li-ion cpu core tft/lcd ccd mcu/rtc i2c/smbus ldo 2 step- down (buck) channels inverter channel system control and monitoring reset output power good reset input +0.8v to 0.9 x vin (prog.) @ 2a memory, i/o step-up (boost) channels +0.8v to 0.9 x vin (prog.) @ 2a +3.3v @20ma step-up (boost) channels
SMB110 preliminary information summit microelectronics, inc 2099 2.3 5/3/2005 2 table of contents general descr iption ........................................................ 3 typical application .......................................................... 4 internal bloc k diagr am.................................................... 5 pin descrip tions ...........................................................6-8 package and pin c onfiguration ...................................... 9 absolute maximu m ratings .......................................... 10 recommended operati ng conditions........................... 10 dc operating charac teristics ..................................10-13 ac operating charac teristics .................................14-15 i 2 c 2-wire serial interface ac operating characteristics- 100khz........................................................................... 16 timing diagrams: i 2 c .................................................... 16 efficiency graphs.......................................................... 17 transient response...................................................... 18 timing diagrams: po wer-on sequence ....................... 19 applications information: device operation power s upply................................................................ 20 enable ........................................................................... 20 power-on sequencing.................................................. 20 normal sequ encing ...................................................... 20 sequencing with enable............................................... 20 sequencing with ch annel bypass ................................. 21 manual m ode ................................................................ 21 monitori ng ..................................................................... 21 output voltage .............................................................. 21 ldo standby voltage ................................................... 22 soft start ....................................................................... 22 power-on sequencing flow chart ................................ 23 minimum load .............................................................. 24 marginin g ...................................................................... 24 application schematic................................................... 25 bill of mate rials.........................................................26-27 programming information development hardwa re & softw are ............................. 28 serial inte rface.............................................................. 29 write.............................................................................. 29 read.............................................................................. 29 configuration registers ................................................ 29 general purpos e memo ry............................................. 29 gui................................................................................ 30 i 2 c memory read and writes ......................................... 31 default configuration register setting .................... . 32 part marking.................................................................. 33 package ........................................................................ 34 ordering info rmatio n ..................................................... 35 legal noti ce .................................................................. 35
SMB110 preliminary information summit microelectronics, inc 2099 2.3 5/3/2005 3 the SMB110 is a fully programmable dc-dc controller that monitors, margins, and cascade sequences. it has 5 voltage outputs, consisting of: two synchronous ?buck? step-down controllers, one ? boost? step-up controller, one ?boost-buck? negative dc-dc controller, and one ldo. the SMB110 uses a fixed 800 khz pulse width modulation (pwm) control circuit. a type three voltage mode compensation network is used offering a cost effective solution without compromising the transient response. by utilizing exte rnal n and p?type mosfet transistors the efficiency and load current can be customized to fit a wide arra y of system requirements. the SMB110 integrates two buck outputs that are capable of producing an output voltage less than the input voltage. each buck output voltage is set by an internal resistor divider and a programmable voltage reference. the integrated resistor divider eliminates the cost and space necessary for external components and has several programmable values. through the programmability of the reference and the resistor divider, practically any output voltage less than the battery can be produced without the need to change external components. in addition, the SMB110 integrates one boost output capable of producing an output voltage greater than the input voltage. the boost topology is asynchronous, using a rectifying schottky diode and eliminating the need for an additional external mosfet driver. an external p- channel sequencing mosfet?s accompanies the boost channel in order to isolate the switching mosfet from the battery when disabled. the SMB110 also contains one inverting buck-boost output capable of producing a negative output voltage less than or greater than, the input voltage. the buck boost output is asynchronous and drives an external p- channel mosfet. a low dropout linear regulator with fixed 3.3 volt output provides a low current supply for ?always on? microcontrollers. the ldo has a special input supply that is internally multiple xed between the ldo supply pin and the battery. this ensures that the ldo will always be active over the recommended operating voltages (2.7v ? 6.0v). the SMB110 is capable of power-on/off cascade sequencing where each channel can be assigned one of four unique sequence positions. during sequencing each channel in a given sequence position is guaranteed to reach its programmed output voltage before the channel(s) occupying the next sequence position initiate their respective soft-start sequence. a unique programmable delay exists between each power on/off sequence position. in addition to power on/off sequencing all supplies can be powered on/off individually through an i 2 c command or by assertion of an enable pin. each output voltage is monitored for under-voltage and over-voltage (uv/ov) conditions, using a comparator- based circuit where the output voltage is compared against an internal programmable reference. an additional feature of the output voltage monitoring is a programmable glitch filter cap able of digitally filtering a transient ov/uv fault conditi on from a true system error. when a fault is detected for a period in excess of the glitch filter, all supplies may be sequenced down or immediately disabled and one of two output status pins can be asserted. the current system status is always accessible via internal regist ers containing the status of all four channels. the SMB110 possesses an undervoltage lockout (uvlo) circuit to ensure the SMB110 will not power up until the battery voltage has reached a safe operating voltage. the uvlo function exhibits hysteresis, ensuring that noise or a brown out voltage on the supply rail does not inadvertently lead to a system failure. the SMB110 provides margining control over all of its output voltages. through an i 2 c command, all outputs can be margined to any voltage setting within the nominal output voltage rage. margining creates three pre-programmed settings that each channel can be set to via an i 2 c command. margining is ideal when used with the boost channel configured as an led driver where margining provides three brightness settings. in addition, each output is sl ew rate limited by soft-start circuitry that is user programmable and requires no external capacitors. all programmable settings on the SMB110 are stored in non-volatile registers and are easily accessed and modified over an industry standard i 2 c serial bus. for fastest prototype development times summit offers an evaluation card and a graphical user interface (gui). general description
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 4 SMB110 comp2_ch3 vm_ch3 gnd vbatt nreset sda scl +0.8v to 0.9 x vin @ 2a 1.1 x vin to 10 xvin @ up to 1a +2.7 to +6.0v vddcap comp2_ch1 comp1_ch1 lsdrv_ch0 vrefout comp2_ch0 -0.8v to -10 x vin @ up to 1a hvsup3 comp1_ch0 pwren0 lsdrv_ch3 lsdrv_ch1 comp1_ch3 hsdrv_ch3 comp2_ch2 vm_ch2 +0.8v to 0.9 x vin @ 2a hvsup2 lsdrv_ch2 comp1_ch2 hsdrv_ch2 pchseq_ch1 host_reset drvgnd healthy vstandby ldo_supply 3.3v @ 20ma typical application figure 2 ? typical application schematic showing external circuitry necessary to configure the SMB110 channels as: step-up, step-down, and inverting outputs
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 5 internal block diagram channel 5 deadtime + ? oa level shifter + ? glitch filter glitch filter clamp duty cycle limit over voltage detection 100k max limit low limit + ? oa level shifter glitch filter glitch filter clamp duty cycle limit max limit low limit sequencing logic enable enable enable digital to analog converter driver + ? + ? over voltage detection over voltage detection under voltage detection under voltage detection under voltage detection lsdrv0 comp1_ch0 channel 0 negative pwm converter channel 2 and 3 synchronous buck pwm converter channel 1 boost pwm converter with shutoff hsdrv[2,3] lsdrv[2,3] pchseq_ch1 lsdrv1 vbatt comp1_ch[2,3] comp2_ch[2,3] comp1_ch1 comp2_ch1 vstandby vm_ch[2,3] vref vref vref vref osc fixed 800khz osc fixed 800khz osc fixed 800khz max limit low limit z z z z z z z z z z z z ldo_supply z + ? pwren0 + ? oa level shifter + ? + ? glitch filter glitch filter clamp duty cycle limit gnd hvsup[2,3] vdd_cap comp2_ch0 x2 vref_out level shifter vref scl sda i 2 c/smbus + ? level shifter + ? zz dq z 2.5v regulator vdd_cap uv2 z uv1 100u + ? comp driver 0.2 v z ldo nbatt_fault bandgap vref standby series-pass ldo vcc_all z z z + ? + ? + ? + ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 6 pin descriptions pin number pin type pin name pin description 1 out healthy the healthy pin is an open drain output. high when all enabled output supplies are within the programmed levels. healthy will ignore any disabled supply. there is a programmable glitch filter on the under-voltage and over-voltage sensors so that short transient s outside of the limits will be ignored by healthy. when used this pin should be pulled high by an external pull-up resistor. 2 i/o sda sda (serial data) is an open drain bi-directional pin used as the i 2 c data line. sda must be tied high through a pull-up resistor. 3 in scl scl (serial clock) is an open drain input pin used as the i 2 c clock line. scl must be tied high through a pull-up resistor. 4 out vref_out the vref_out (voltage reference) pin is a precision reference output. when an inverting output is used, this pin acts as a level shifting reference for the feedback circuitry. when the inverting output is not used, this pin may be used as a programmable reference. 5 in comp1_ch0 comp1_ch0 (channel 0 primary compensation) pin is the primary feedback input of the inverting controller. 6 in comp2_ch0 comp2_ch0 (channel 0 secondary compensation) pin is the second feedback input of the inverting controller 7 out lsdrv_ch0 the lsdrv_ch0 (channel 0 lo w-side driver) pin is the switching node of the inverting buck-boost controller. the output of this pin should be attached to the gate of an external p- channel mosfet driver. 8 in host_reset the host_reset pin is an active high reset input. when this pin is asserted high, the nreset output will immediately go low. when host_reset is brought low, nreset will go high after a programmed reset delay. 9 cap vbatt_cap the vbatt_cap (vbatt capacito r) pin is an external capacitor input used to filter the internal supply. 10 pwr vbatt power supply to part. 11 out pchseq_ch1 the pchseq_ch1 (channel 1 sequence) pin is attached to an external p-channel mosfet and is used to enable the corresponding channel 1 boost controller. pchseq_ch1 uses an internal 100 p a current sink for sequencing. this pin should be pulled high through a parallel rc connection. 12 in comp1_ch1 the comp1_ch1 (channel 1 primary compensation) pin is the primary compensation input of the channel 1 boost controller. 13 in comp2_ch1 the comp2_ch1 (channel 1 secondary compensation) pin is the second compensation input of the channel 1 boost controller.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 7 pin descriptions pin number pin type pin name pin description 14 out nreset the nreset (reset) pin is an acti ve low open drain output. active when the SMB110 is powered up. remains low for a user programmable period of 25, 50, 100, or 200 ms after all enabled supplies have exceeded their programmed thresholds. when used, this pin should be pulled high by an external pull up resistor. 15 pwr drvgnd drvgnd (driver ground). each drvgnd pin should be attached externally to ground through a short wide wire. 16 out lsdrv_ch1 the lsdrv_ch1 (channel 1 low-side driver) pin is the lower switching node of the synchronous boost controller. this pin attaches to an external n-channel mosfet 17 out lsdrv_ch2 the lsdrv_ch2 (channel 2 low-si de driver) pin is the lower switching node of the channel 2 sync hronous buck controller. attaches to the gate of n-channel mosfet. 18 pwr hvsup2 supply for channel 2 buck driver. 19 out hsdrv_ch2 the hsdrv_ch2 (channel 2 high-side driver) pin is the upper switching node of the channel 2 synchronous buck controller. attach to the gate of p-channel mosfet. a del ay exists between the assertion of hsdrv_ch2 and assertion of lsdrv_ch2 to prevent excessive current flow during switching. 20 in comp2_ch2 the comp2_ch2 (channel 2 secondary compensation) pin is the secondary compensation input of the channel 2 buck controller. 21 in comp1_ch2 the comp1_ch2 (channel 2 primary compensation) pin is the primary compensation input of the c hannel 2 buck controller. each pin is internally connected to a programmable resistor divider. 22 in vm_ch2 the vm_ch2 (channel 2 voltage moni tor) pin connects the channel 6 controller output. internally the vm_ch2 pin connects to an internal programmable resistor divider. 23 pwr ldo_supply the ldo_ supply pin powers the 3.3v vstandby ldo output. the ldo_ supply pin should be connected to the output of a boost output (usually the intermediate bus). when the battery voltage drops below the uv1 threshold, this pin will no longer supply the ldo. do not apply a voltage in excess of the recommended input voltage to this pin. 24 out vstandby the vstandby (voltage standby) pin is a 3.3v ldo output. vstandby is supplied from the ou tput of the intermediate bus through the ldo_supp pin. when pwr_fail is asserted an internal analog multiplexer will power vstand by directly from the vbatt pin. 25 out lsdrv_ch3 the lsdrv_ch3 (channel 3 low-si de driver) pin is the lower switching node of the channel 3 sync hronous buck controller. attaches to the gate of n-channel mosfet. 26 pwr hvsup3 supply for channel 3 buck driver.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 8 pin description pin number pin type pin name pin description 27 out hsdrv_ch3 the hsdrv_ch3 (channel 3 high-si de driver) pin is the upper switching node of the channel 3 sy nchronous buck controller. attach to the gate of p-channel mosfet. a delay exists between the assertion of hsdrv_ch3 and assert ion of lsdrv_ch3 to prevent excessive current flow during switching. 28 in pwren0 the pwren0 (power enable 0) pin is a programmable input used to enable (disable) selected supplies. when unused this pin should be tied to a solid logic level. 29 in comp2_ch3 the comp2_ch3 (channel 3 secondary compensation) pin is the secondary compensation input of the channel 3 buck controller. 30 in comp1_ch3 the comp1_ch3 (channel 3 primary compensation) pin is the primary compensation input of the channel 3 buck controller. each pin is internally connected to a programmable resistor divider. 31 in vm_ch3 the vm_ch3 (channel 3 voltage moni tor) pin connects the channel 3 controller output. internally the vm_ch3 pin connects to an internal programmable resistor divider. 32 pwr gnd the gnd pin should be connected to the common ground plane through a short fat wire. pad pwr gnd the exposed metal pad should be attached to ground.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 9 comp2_ch3 1 gnd 2 3 13 vm_ch3 4 vm_ch2 10 hsdrv_ch3 12 11 28 27 26 scl comp1_ch0 comp1_ch1 comp1_ch2 comp2_ch2 5 6 7 8 comp2_ch0 lsdrv_ch0 9 comp1_ch3 lsdrv_ch3 comp2_ch1 24 23 22 25 17 14 16 vddcap 15 18 20 pchseq_ch1 21 hvsup2 hsdrv_ch2 lsdrv_ch2 19 gnd sda hvsup3 vbatt 32 31 30 29 pwren0 drvgnd lsdrv_ch1 nreset vref_out healthy host_reset ldo_supply vstandby package and pin description top view SMB110 5mm x 5mm qfn-32
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 10 absolute maximum ratings recommended operating conditions temperature under bias .................... -55 c to +125 c storage temper ature.......................... -65 c to +150 c terminal voltage with respect to gnd: vbatt supply voltage ................... -0.3v to +6.5v hvsup supply voltage .................. -0.3v to +6.5v ldo_supply ................................ -0.3v to +6.5v all others ...................................... -0.3v to vbatt output short circuit current .................????100ma reflow solder temp erature (30 secs)................. 260 c junction temperature.......................................... 150 c esd rating per jedec ....................................... 2000v latch-up testi ng per je dec............................. 100ma commercial temperature range............... 0c to +70c vbatt supply voltage .............................. 2.7v to +6.0v hvsup supply voltage ..............................2.7v to +6.0v ldo_supply........................................... gnd to +6.0v all others................................................. gnd to vbatt package thermal resistance ( t ja ) 32 lead qfn. ???..?????..?????... ?tbd moisture classification level 3 (msl 3) per j-std- 020 reliability characteristics data retentio n ................................................. 100 years endurance ..................................................100,000 cycle temperature range 0c to +70c note - the device is not guaranteed to function outside it s operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions outside those listed in t he operational sections of the specification is not implied. exposure to any absolute maximum rating for extended period s may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended. dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit vbatt input supply voltage input supply voltage (operational) 2.7 6.0 v v ldo_supp linear regulator supply voltage internally multiplexed with vbatt 2.7 6.0 v v hvsup buck driver supply voltage gate drive voltage 2.7 6.0 v vbatt rising 2.2 v uvlo undervoltage lockout vbatt falling 2.0 v i dd-monitor monitoring current all voltage inputs monitored. no supplies switching, vbatt at 4.2v, ldo on with no output enabled 330 a i sd switching current for one output enabled current drawn when one output enabled 1.2 ma i dd- total current all channels switching. 1 vbatt at 4.2v, ldo on with no load 2.2 ma v ref(int) internal voltage reference 0.995 1.005 v oscillator f osc oscillator frequency 800 khz ? ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 11 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit error amplifier v acc threshold voltage accuracy 0.2 % ts temperature stability 0.2 % a vol open loop voltage gain at dc 60 db bw frequency bandwidth at av=0 db 30 mhz i source output source current at 0.5v 20 a i sink output sink current at 0.5v 800 a ldo v out nominal output voltage ldo_supply = 4.2v, i load =0a 3.3 v ? ? ? ? ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 12 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit inverting output block channel 0 (continued) i ref_out vref_out source current vref_out = 1.5v 100 a ml minimum load 3 l=33uf, v o =-7.5v, v in =4.2v, v d =0.3v 10.1 k ? ? ? ? ? a en th enable threshold voltage on pchseq pin when lsdrv output is enabled 200 mv buck output block channels 2 and 3 vbatt = 4.2v, i load = 0 0.5 3.8 v out voltage nominal set point range vbatt = 6.0v, i load = 0 0.6 5.4 v ? ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 13 dc operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit miscellaneous v ih input high voltage 0.9xvdd_cap v v il input low voltage 0.1xvdd_cap v v ol open drain outputs i sink = 1ma 0 0.4 v i ol output low current 0 1.0 ma programmable monitoring thresholds v puv1 programmable uv1 threshold programmable uv1 threshold voltage measured on vbatt pin in 150 mv increments 2.55 3.60 v ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 14 ac operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit 1.3 1.5 1.7 10.6 12.5 14.4 21.3 25 28.8 t ppto programmable power-on sequence timeout period. programmable power-on sequence position to sequence position delay. 42.5 50 57.5 ms 1.3 1.5 1.7 10.6 12.5 14.4 21.3 25 28.8 t dpoff programmable power-off sequence timeout period. programmable power-off sequence position to sequence position delay. 42.5 50 57.5 ms 21.3 25 28.8 42.5 50 57.5 85 100 115 t prto programmable reset time-out delay programmable time following assertion of last supply before nreset pin is released high. 170 200 230 ms off 42.5 50 57.5 85 100 115 t pst programmable sequence termination period time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. if exceeded, a force shutdown will be initiated. 170 200 230 ms 0 t pgf programmable glitch filter period for which fault must persist before fault triggered actions are taken. present on all buck, boost, and inverting supplies. 6.8 8 9.2 p s 340 400 460 170 200 230 85 100 115 56.7 66.7 76.7 42.5 50 57.5 28.3 33.3 38.3 21.3 25 28.8 sr ref programmable slew rate reference adjustable slew rate factor proportional to output slew rate. 17.0 20 23 v/s
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 15 ac operating characteristics (continued) (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter conditions min typ max unit inverting output block channel 0 t rh hs driver output rise time c g =100pf, vbatt=4.2v 10 ns t fh hs driver output fall time c g =100pf, vbatt=4.2v 10 ns boost output block channel 1 t rl ls driver output rise time c g =100pf, vbatt=4.2v 10 ns t fl ls driver output fall time c g =100pf, vbatt=4.2v 10 ns buck output block channels 2 and 3 t rl ls driver output rise time c g =100pf, vbatt=4.2v 10 ns t fl ls driver output fall time c g =100pf, vbatt=4.2v 10 ns t rh hs driver output rise time c g =100pf, vbatt=4.2v 15 ns t fh hs driver output fall time c g =100pf, vbatt=4.2v 5 ns high to low transition on hsdrv 20 t dt driver non-overlap delay low to high transition on buck hsdrv 10 ns v ref_out -.95(1+r2/r1) v ref_out - (1+r2/r1) % n= 1,2,3,4 ch 0 p uvth = -100n 1 - 3. the minimum load for the inverting boost-buck channel is defined by the following equation: where v o = programmed output voltage, vin =p- channel mosfet source voltage, l = inductance, vd = forward dio de drop (0.6v silicon, 0.3v schottky). lesser values may exist 4. the minimum load for boost channels is defined by the following equation: where v o = programmed output voltage, vin =p-channel mosfet source voltage, l = inductance, and vd = forward diode drop (0.6v silicon, 0.3v schottky. lesser values may exist 6. the channel 0 programmable over voltage setting is calculated fr om the following formula: where vref_out is the voltage o th e vref_out pin and r1 and r2 are the u pp er and lower resistors in the external volta g e divider , n corres p onds to the available user p ro g rammable settin g s 5. the channel 0 programmable under voltage setting is calculated fr om the following formula: where vref_out is the voltage o t he vref_out p in and r1 and r2 are the u pp er and lower resistors in the external volta g e divider , n corres p onds to the available user p ro g rammable settin g s v ref_out -.95(1+r2/r1) v ref_out - (1+r2/r1) % n= 1,2,3,4 ch 0 p ovth = 100n 1 - 2*l*vout *(vout - vd) rmax = vin 2 * 1.25e-8 2*l*vout*(vout - vin + vd) vin 2 * 1.25e-8 rmax = 1. the total current drawn when all s upplies are switching will not equal the sum of the buck, boost, and inverting buck-boost channels current consumption when switching independently. this is due to current overhead to commence sequencing. 2. guaranteed by design.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 16 note: 1 / - guaranteed by design. figure 4 ? i 2 c timing diagram i 2 c-2 wire serial interface ac ope rating characteristics ?100 khz (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) 100khz symbol description conditions min typ max units f scl scl clock frequency 0 100 khz t low clock low period 4.7 p s t high clock high period 4.0 p s t buf bus free time before new transmission - note 1 / 4.7 p s t su:sta start condition setup time 4.7 p s t hd:sta start condition hold time 4.0 p s t su:sto stop condition setup time 4.7 p s t aa clock edge to data valid scl low to valid sda (cycle n) 0.2 3.5 p s t dh data output hold time scl low (cycle n+1) to sda change 0.2 p s t r scl and sda rise time note 1 / 1000 ns t f scl and sda fall time note 1 / 300 ns t su:dat data in setup time 250 ns t hd:dat data in hold time 0 ns ti noise filter scl and sda noise suppression 100 ns t wr_config write cycle time config configuration registers 10 ms t wr_ee write cycle time ee memory array 5 ms timing diagrams t r t f t high t low t su:sda t hd:sda t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t wr (for write operation only) timing diagrams
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 17 channel 0 inverting -7.5v 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0 0.01 0.02 0.03 0.04 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v channel 2 buck 2.5 volts 0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0 0.1 0.2 0.3 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v efficiency graphs channel 1 boost 6.0v 0.78 0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96 0 0.2 0.4 0.6 0.8 1 current (amps) efficiency 4.2v 3.8v 3.6v 3.0v channel 3 (ch 1 boost + buck) 3.0 volts 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.01 0.11 0.21 0.31 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v ( all measurements are taken at 25c, and are based on the a pp lications schematic. ) channel 3 (ch 1 boost + buck) 5.0 volts 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 0 0.1 0.2 0.3 0.4 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v channel 2 buck 1.2v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.2 0.4 0.6 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v channel 1 boost 12v 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0 0.01 0.02 0.03 current (amps) efficiency 3.0v 3.3v 3.6v 3.8v 4.2v
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 18 channel 2 buck transient response v in = 4.2v v out = 5.0v v in = 4.2v v out = 1.2v v in = 4.2v v out = 2.5 v in = 4.2v v out = 3.0v 0v 0a 0v 0v 0v 0v 0v 0 a 0 a 0 a 0 a 0 a channel 2 buck transient response channel 3 buck transient response channel 3 buck transient response channel 0 inverting transient response v in = 4.2v v out = -7.5v v in = 4.2v v out = 12v channel 1 step up transient response 200 us/div 200 us/div 200 us/div 200 us/div 200 us/div 200 us/div i sd 100ma/div v su ac-coupled 50mv/div i sd 5ma/div i sd 10ma/div i sd 100ma/div i sd 200ma/div i sd 100ma/div transient response ( all measurements are taken at 25c, and are based on the a pp lications schematic. ) v su ac-coupled 50mv/div v su ac-coupled 50mv/div v su ac-coupled 50mv/div v su ac-coupled 50mv/div v su ac-coupled 50mv/div
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 19 vbatt intermediate boost pwren0 or i 2 c enable step-up,step-down, or inverting output healthy sequence delay step-up,step-down, or inverting output nreset vstandby sequence position 123 t reset timeout 0 4 pwren0 or i 2 c enable pwren0 or i 2 c enable step-up,step-down, or inverting output pwren0 or i 2 c enable timing diagrams: power-on sequence figure 5 ? SMB110 power-on sequence. any pwm channel may be enabled or disabled through an i 2 c command or by the pwren0 pin.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 20 applications information device operation power supply the SMB110 can be powered from an input voltage between 2.7-6.0 volts appli ed between the vbatt pin and ground. the input voltage applied to the vbatt pin is internally regulated and used as an internal vbatt supply. the vbatt pin is monitored by an undervoltage lockout (uvlo) circuit, which prevents the device from turning on when the voltage at this node is less than the uvlo threshold. power-on/off control the outputs on the SMB110 can be turned on in one of three ways: first a general purpose enable input pin pwren0, second an i 2 c power on command can be issued, or third if a programmable bit is set to initiate the power on process when the uvlo threshold is exceeded. a restart will only oc cur if the power-on pin is toggled or an i 2 c p ower on command is issued. enable once a power on command has been issued, the power on process can be controlled by means of an enable signal. each channel can be controlled by one of four enable signals and the assignment type can be mixed and matched for each of the four channels. the enable signal can stall the power-on process until the enable is valid, or disable a controller once all supplies have been enabled. there are two ways to generate the enable signal; the first approach allows the enable signal to be assigned the pwren0 pin, and the second approach allows the enable to be controlled by the contents of a volatile regist er that can be written to at any time. this volatile register will be automatically initialized once the uvlo threshold has been exceeded to a known programmed state. power-on sequencing each channel on the SMB110 may be placed in any one of four unique sequence positions. to provide programmable order, the SMB110 navigates between these sequence positions using a feedback-based cascade-sequencing circuit. cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. once power-on sequencing has been initiated, automated sequencing may commence in one of three ways (figure 7): normal sequencing, sequencing with enable, and sequencing with channel bypass. in addition, each channel may be powered on in a manual mode, independent of the sequence position. the power-on sequencing mode selection is programmable over the i 2 c bus and stored in the non-volatile memory. normal cascade sequencing during normal sequencing , the sequence position counter is initialized to the first sequence position (position 1), each channel occupying this position then waits an individual programmable timeout period (t ppto ) of 1.5, 12.5, 25, or 50 ms. once enabled, all channels occupying the firs t sequence position will begin a soft- start. as the output voltage of the channel is ramped up, it is monitored by a comparator based, user programmable, under-voltage threshold sensor. after this threshold is exceeded, indicating that the selected channel(s) have reached their nominal operating range the sequence position counter is incremented, and fault monitoring begins for that channel. once all channels occupying the first sequence position have surpassed their under-voltage thresholds, the power-on delay for the next sequence position will begin. this process continues until all channels have been sequenced on and are above their under-voltage threshold. sequencing with enable during the sequencing with enable mode, sequencing commences as with the normal sequencing , except that prior to a channel beginning to soft-start, the enable corresponding to that c hannel must be asserted. in the event that the enable is not asserted, sequencing will halt indefinitely until a valid enable is provided. once a valid enable is provided, a soft-start function will begin for that channel. this pr ocess will continue until all channels occupying the first sequence position are above their under-voltage settings, at which point the sequence position counter will be incremented. sequencing with channel bypass when the sequencing with channel bypass mode is selected, sequencing will commence as with the sequencing with enable , except that if the enable signal is not asserted by the end of the power-on delay period, that channel will be bypassed. if no other channels occupy the current sequence position, the sequence position counter will be incremented beginning the power-on delay for all channels in the next sequence position. once a channel has been bypassed, it may still be enabled any time prior to a power off operation.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 21 applications information (continued) manual mode the SMB110 also provides a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. in this mode, the enable has complete control over the channel, and all sequencing is ignored. in manual mode channels will not be disabled in the event of a fault. power off options force-shutdown when a battery fault occurs, a uv or ov is detected on any pwm channel, or an i 2 c force-shutdown command is issued, all channels will be immediately disabled. sequence termination timer at the beginning of each s equence position, an internal programmable timer will begin to time out. when this timer has expired, the SMB110 will automatically perform a force-shutdown operation. this timer is user programmable with a programmable sequence termination period (t pst ) of 50,100,200 ms; this function can also be disabled. power off sequencing the SMB110 has a power-off sequencing operation. during a power off operati on the supplies will be powered off in the reverse order they where powered on in. during the power off sequencing, all enables are ignored. when a power-off command is issued the SMB110 will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequenc e position will begin to timeout, after which that channel(s) will be disabled. this process will continue until all channels have been disabled and are off. th e programmable power-off sequence timeout period (t dpoff ) can be set to 1.5, 12.5, 25, or 50 ms. if a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. monitoring the SMB110 monitors all 4 pwm outputs for under- voltage (uv) and over-voltage (ov) faults. the monitored levels are user programmable, and may be set at 5,10, 15, and 20 percent of the nominal output voltage. each output possesses a glit ch filter to ensure that short violations in the uv or ov settings will not result in a fault-triggered action. all glitch filters on the SMB110 are user programmable and may be set to either 0 or 8 s. in the event that one or mo re channels violate their respective uv/ov setting for a period exceeding that specified by the glitch filter, all channels (not set to manual mode) can optionally be powered off and-or, the healthy pin can be triggered. the programmable power off conditions that may result from a threshold violation include the immediate power off all supplies (force-shutdown) or the se quence of all supplies off. monitoring is accomplish ed by a comparator-based approach, in which a programmable voltage reference is compared against the monitored signal. each channel possesses a dedicated reference voltage generated by a programmable level shifting digital to analog converter. each of which can be set from 0-1.0 volts in 4mv increments. battery monitoring the battery voltage is monitored for two user programmable uv settings via the vbatt pin the SMB110 contains two user programmable voltage- monitoring levels, uv1 and uv2. battery voltage, like all monitored voltages, is compared against a user programmable voltage set internally by a digital to analog converter. once the voltage on the vbatt pin has fallen below either of the programmable under voltage set points the SMB110 can be programmed to respond in one of three ways, it can perform: a power-off operation, a force-shutdown operation, or take no action. when programmed to perform a pow er-off or force-shutdown operation the SMB110 can optionally be programmed to latch the outputs off until an i 2 c power-on command is issued or immediately restart once the uv condition has been removed. output voltage the pwm output voltages are set by a resistor divider from the output to the comp1 node; see figure 6. for the buck channels (ch[2:3]), the voltage divider is internal to the part and programmable. the resistor divider may be set by adjusting a 100 k ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 22 applications information (continued) voltage, which varies from 1.0 ? 2.0v in 8 mv increments ldo standby voltage the SMB110 has an internal 3.3 volt low dropout (ldo) linear regulator. while the battery voltage is above the uv2 level this supply is powered from the ldo_supply pin, however, when the battery voltage drops below the uv2 level the ldo supply voltage will be routed to the battery through an internal analog multiplexer. the ldo will continue to be supplied by the battery until the latched uv2 pin is released. the ldo will be disabled once the battery voltage falls below the uv2 level. soft start the SMB110 provides a programmable soft-start function for all pwm outputs. the soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. the soft start slew rate is proportional to the product of the output voltage and a slew rate reference; see figure 5. this global reference is programmable and may be set to 400,200,100,67,50,33,25, and 20 volts per second. the slew rate control can also be disabled on any channel not requiring the feature. r1 comp1 vref r1 r2 comp1 vout r2 1.0v vout vref_out channel 0 channels 1 to 3 r1 and r2 internal for channels 2 and 3 + ? + ? figure 6: the output voltage is set by the resistor divider . the resistor divider is internal for all buck channels. vref is programmable from 0 to 1.0v in 4 mv increments and vref_out is programmable from 1.0 to 2.0v in 8 mv increments. all voltage references are programmable via the i 2 c interface.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 23 figure 7 ? power-on sequencing flow chart: there are three automated power-on sequencing modes, and a manual mode. applications information (continued) restart after pow er- off or force-shutdow n i 2 c pow er on command begin sequencing sequence position 1 normal sequencing current sequence position sequencing w ith enable sequencing w ith channel bypass enable = pw ren0 pin xor i2c pw r enable bit channel-specific program m able options enable = pw ren0 pin xor i2c pw r enable bit pow er on delay pow er on delay pow er on delay next sequence position wait for enable enable lo w enable high enable lo w enable high soft- start wait for enable vo u t<=uv monitor vo ut<=uv soft- start enable high enable lo w
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 24 minimum load the duty cycle is limited to a 10-90% range. consequently, the boost channels require a minimum load to prevent over voltage conditions from occurring. this may be overcome by attaching a resistor preload to the output that matches the minimum load requirements. this approach will result in a constant current consumption while the outputs are enabled. alternatively, a zener diode (with a higher breakdown voltage than the output) can be connected across the output clamping the output voltage. this approach will not draw current when the load is enabled on the output. margining the SMB110 has two additional voltage settings for channels 0-3, margin high and margin low. the margin high and margin low voltage settings have the same voltage range as the controllers? nominal output voltage. these settings ar e stored in the configuration registers and are loaded into the voltage setting by margin commands issued via the i 2 c bus. the margin command registers contain two bits for each channel that decode the commands to margin high, margin low, or control to the nominal setting. therefore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. once the SMB110 receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. when all channels are at their voltage setting, a bit is set in the margin status registers. note: configuration writes or reads of registers should not be performed while margining. a typical application utilizing the margining functionality is depicted in figure 8. when used with a boost controller setup as a constant current white led driver, margining can be used to adjust the current through the led chain as an adjustable brightness control. fi g ure 8 ? boost confi g ured as a constant current white led driver with ad j ustable current ca p abilities. SMB110 boost vin pchseq lsdrv comp1(0-1.0v) comp2 applications information (continued)
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 25 applications information (continued) figure 9 ? applications schematic. channel 3 setpoint 5.0v programmable from 0.8v to .9 x vbatt vbatt channel 0 setpoint -7.45v programmable from -0.8v to -9 x vbatt r12 10 c39 10uf reset# r13 10 imbus c32 10uf channel 2 setpoint 3.3v programmable from 0.8v to .9 x vbatt c33 0.1uf r17 10 r18 10 healthy 1 sda 2 scl 3 vref_out 4 comp1_ch0 5 comp2_ch0 6 lsdrv_ch0 7 host_reset 8 vddcap 9 vbatt 10 pchseq_ch1 11 comp1_ch1 12 comp2_ch1 13 nreset 14 drvgnd 15 lsdrv_ch1 16 lsdrv_ch2 17 hvsup2 18 hsdrv_ch2 19 comp2_ch2 20 comp1_ch2 21 vm_ch2 22 ldo_supply 23 vstandby 24 lsdrv_ch3 25 hvsup3 26 hsdrv_ch3 27 pwren0 28 comp2_ch3 29 comp1_ch3 30 vm_ch3 31 gnd 32 u2 SMB110 sda scl vbatt r19 100k r2 12k c27 0.01uf r9 10 c22 1800pf c23 2700pf c24 100pf c5 22uf r14 90k 2.7 to 5.5v vref_out r15 432 r3 12k r4 365 r24 47k c12 2700pf c13 68pf c14 1000pf l6 inductor ferrite healthy r16 15k c38 0.1uf vbatt r20 47k l3 33uh d3 diode schottky c18 22uf c34 0.1uf c35 10uf c15 3300pf c30 10uf r27 47k c31 0.1uf pwren0 vbatt r22 47k l2 6.8uh place close to part imbus imbus q2(p) q1(n) q4 mosfet dual r5 316 3.3v ldo c7 22uf r6 392k c43 0.1uf c44 10uf l4 33uh q2 mosfet p c1 0.1uf c2 1uf r7 33k q2(p) q1(n) q3 mosfet dual r8 11k c28 10uf c29 0.1uf c16 100pf l1 6.8uh c17 3300pf vbatt r23 47k imbus d4 diode schottky channel 1 setpoint 5.5v programmable from 0.8v to .9 x vbatt r1 365 vbatt c9 2700pf host_reset r21 6.8k c25 22uf q2(p) q1(n) q1 mosfet dual vbatt c10 68pf vbatt r10 10 c11 1000pf c20 10uf r11 10
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 26 applications information (continued) item description- vendor / part number qty ref. des. resistors 1 365 ? ? ? ? ? ? ? ? ? ? ? ? ?
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 27 applications information (continued) item description- vendor / part number qty ref. des. 29 inductor, 33uh, smd coilcraft do1608c-333 or asatech 33uh 3 l2, l3, l8 30 inductor, 6.8uh, smd sumida corp cr436r8 or coilcraft do1608c-682 or asatech 6.8uh 3 l4, l5, l7
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 28 development hardware & software the end user can obtain the summit smx3200 parallel port programming system or the i 2 c2usb (smx3201) usb programming system for device prototype development. the smx3200(1) systems consists of a programming dongle, cable and windows tm gui software. it can be ordered on the website or from a local representative. the late st revisions of all software and an application brief describing the smx3200 and smx3201 are available from the website ( http://www.summitmicro.com ). the smx3200 programming dongle/cable interfaces directly between a pc?s parallel port and the target application; while the smx3201 interfaces directly to the pc?s usb port and the target application. the device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the SMB110 via the programming dongle and cable. an example of the connection interface is shown in figure 11. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper device operation in the end application. pin 9, 5.0v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, reserved pin 10, reserved top view of straight 0.1" x 0.1 closed-side connector. smx3200(1) interface cable connector. 9 7 5 3 1 10 8 6 4 2 SMB110 sda scl gnd 0.1 p f figure 10 -- smx3200(1) programmer i 2 c serial bus connections to program the SMB110.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 29 i 2 c programming information serial interface access to the configurati on registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (i 2 c). sda is a bi-directional data line and scl is a clock input. data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers, sda must remain stable while scl is high. data is transferred in 8- bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating start and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 7-bit device type identifier (slave address). the remaining bit indicates either a read or a write operation. refer to t able 1 for a description of the address bytes used by the SMB110. the device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. the slave address can be can be programmed to any seven bit number 0000000 bin through 1111111 bin . write writing to the memory or a configuration register is illustrated in figures 11 and 12. a start condition followed by the slave address byte is provided by the host; the SMB110 responds with an acknowledge; the host then responds by sending the memory address pointer or configuration r egister address pointer; the SMB110 responds with an ack nowledge; the host then clocks in one byte of data. for memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the non-volatile configuration registers and memory register s as well as the volatile command and status register s must be set before data can be read from the SMB110. this is accomplished by issuing a dummy write command, which is a write command that is not followed by a stop condition. a dummy write command sets the address from which data is read. after the du mmy write command is issued, a start command followed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to fi gure 13 for an illustration of the read sequence. configuration registers the configuration registers are grouped with the general- purpose memory. general-purpose memory the 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. the first 48-byte memory block begins at register address pointer a0 hex and the second memory block begins at the register address pointer c0 hex ; see table 1. each memory block can be locked individually by writing to a dedicated register in the configuration memory space.
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 30 graphical user interface (gui) device configuration utilizing the windows based SMB110 graphical user interface (gui) is highly recommended. the software is available from the summit website ( http://www.summitmicro.com ). using the gui in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3200) is available from summit to communicate with the SMB110. the dongle connects directly to the parallel port of a pc and programs the device through a cable using the i 2 c bus protocol. see figure 7 and the smx3200 data sheet. slave address register type configuration registers are located in 00 hex thru 9f hex general-purpose memory block 0 is located in a0 hex thru bf hex 0000000 bin to 1111111 bin general-purpose memory block 1 is located in c0 hex thru ff hex table 1 ? possible address bytes used by the SMB110. i 2 c programming information (continued)
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 31 s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 11 ?register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 12 ?register page write i 2 c programming information (continued) s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 13 -register read
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 32 the default device ordering number is SMB110nc-323l. it is programmed with the register contents as shown above and tested over the commercial temperature range. the ordering number is derived from t he customer supplied hex file. new device suffix numbers are assigned to non-default requirements. default configuration register settings ? SMB110nc-323l register contents register contents register contents r0 d7 r15 00 r2c 02 r3 60 r16 20 r2d 00 r4 7d r17 00 r2e 39 r5 a5 r18 02 r2f 2e r8 30 r1b 02 r50 cf rb 60 r1c 02 r53 5b rc 50 r1d 02 r54 71 rd 40 r20 30 r57 95 r10 96 r23 30 r58 df r11 5a r24 30 r5b 65 r12 14 r27 30 r5c 8a r13 50 r2a 03 r5d b6 r14 a0 r2b 00
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 33 package
SMB110 preliminary information summit microelectronics, inc 2099 2.3 3/1/2005 34 summit SMB110n ayyww pin 1 annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) l 100% sn, rohs compliant, green notice note 1 - this is a preliminary information data sheet that describes a summit product currently in pre-production with limited characterization. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assu mes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect repres entative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc . shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receive s written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 2.2 - this document supersedes all previous versions . please check the summit microelectronics inc. web site at http://www.summitmicro.com for data sheet updates. ? copyright 2005 summit microelectronics, inc. programmable analog fo r a digital world? adoc tm is a registered trademarks of summit microelectronics inc., i 2 c is a trademark of philips corporation. ordering information part marking SMB110 n package n = 32 pad qfn summit part number specific requirements are contained in the suffix nnn part number suffix l l = 100% sn, rohs compliant, green blank = 85% sn, 15% pb c c = commercial temperature range solder composition

▲Up To Search▲

Price & Availability of SMB110

	To Download SMB110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .